1. Field of the Invention
The present invention relates to a semiconductor device having a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) and a method of manufacturing the semiconductor device.
2. Description of Related Art
A vertical MOSFET is normally used as a power device such as a power MOSFET serving as a power switch for large current and high voltage. In the vertical MOSFET, a source electrode and a gate electrode are formed on a principal surface of a semiconductor chip and a drain electrode is formed on a rear surface thereof. A drain current flows in a longitudinal direction of the semiconductor chip (from the principal surface to the rear surface). In order to suppress power consumption, the power MOSFET requires a minimum ON-resistance. Therefore, there has been developed a vertical MOSFET in which the gate electrode is formed in a trench and a channel region is formed in a longitudinal direction to narrow an interval between gate electrodes, thereby realizing a high density to reduce an ON-resistance per unit area.
In recent years, there has been appeared a chip size package (CSP) in which the source electrode, the gate electrode, and the drain electrode of the vertical MOSFET are formed on a single surface of a semiconductor die. According to a conventional vertical MOSFET disclosed in U.S. Pat. No. 6,653,740 B2, in order to electrically connect a drain region formed in a rear surface of the semiconductor die with the drain electrode formed on the principal surface of the semiconductor die, a high-concentration diffusion region or a buried conductive layer is used.
The conventional vertical MOSFET disclosed in U.S. Pat. No. 6,653,740 B2 will be described with reference to the attached drawings. FIG. 30 is a perspective view showing a semiconductor die 10. FIG. 31 is a cross sectional view showing the semiconductor die 10. FIGS. 32A and 32B are cross sectional views showing other examples of a drain connection portion of the semiconductor die 10.
As shown in FIG. 30, an external source terminal 2, an external drain terminal 3, and an external gate terminal 4 are formed on a principal surface of a silicon body 1. As shown in FIG. 31, gate electrodes 11 are buried in gate trenches 16 and electrically connected with the external gate terminal 4 through a gate wiring 5 shown in FIG. 30.
As shown in FIG. 31, a drift region 6 which is a P-type epitaxial layer is formed in a surface of the P+-type silicon body 1 which is a drain region. An N-type channel region 7 is formed in the drift region 6. P+-type source regions 8 are formed in a surface of the channel region 7. The gate trenches 16 are formed so as to extend through the source regions 8 and the channel region 7 and reach the drift region 6. The gate electrodes 11 are buried in the gate trenches 16 through gate insulating films 12. The gate electrodes 11 are electrically connected with each other and electrically connected with the gate wiring 5 (not shown). Interlayer insulating films 13 are formed on the gate electrodes 11. A source electrode 14 is formed to cover the interlayer insulating films 13. The source electrode 14 has contact holes 17, each of which is formed so as to extend through a part of the source region 8. The source electrode 14 is electrically connected with the source regions 8 through the contact holes 17 and electrically connected with the channel region 7 through N+-type contact diffusion regions 9 formed in bottom surfaces of the contact holes 17. The source electrode 14 is electrically connected with the external source terminal 2 (not shown).
The channel region through which a drain current flows is formed in a longitudinal direction along a side surface of the gate trenches 16. The drain current flows from each of the source regions 8 to the silicon body 1 which is the drain region through the channel region 7 and the drift region 6. In order to lead the drain current flowing into the drain region to a surface of the silicon body 1, a part of the P+-type silicon body 1 is left under a drain electrode 15 and connected with the drain electrode 15. The drain electrode 15 is electrically connected with the external drain terminal 3 (not shown).
FIG. 32A is a partial cross sectional view showing an example of a P+-type high-concentration diffusion region 18 which is another example of a connection portion between the silicon body 1 (drain region) shown in FIG. 31 and the drain electrode 15. FIG. 32B is a partial cross sectional view showing yet another example of the connection portion. In this example, a trench 19 is formed to reach the silicon body 1 (drain region) and a buried conductive layer 20 is formed in the trench 19. As shown in FIGS. 31, 32A, and 32B, a drain current path for connecting the drain region formed on the rear surface side of the silicon body 1 with the drain electrode 15 formed to the principal surface of the silicon body 1 is provided in the silicon body 1 to form the external drain terminal 3 to the principal surface of the silicon body 1.
However, the inventor of the present invention found that the above-mentioned prior art has room for further improvement in view of the ON-resistance.
A length of the drain current path from the drain region to the drain electrode 15 is a length corresponding to a thickness of the drift region 6. The thickness of the drift, region 6 is determined based on a designed withstand voltage of the vertical MOSFET. The thickness depends on, for example, an impurity concentration of the drift region 6 and an impurity concentration and a thickness of the channel region 7. A necessary thickness is, for example, approximately 2 μm to 3 μm. In order to reduce an ON-resistance of the semiconductor device 10, it is necessary to reduce a resistance value of the drain current path. When the silicon body 1 is to be used for the drain current path as shown in FIG. 31 without any modification, it is necessary to increase an impurity concentration of the silicon body 1 or to widen a cross sectional area of the drain current path to reduce a resistance value thereof. However, this is actually difficult.
When the drain current path is to be formed so as to have a low resistance in the deep high-concentration diffusion region 18 as shown in FIG. 32A, it is necessary to perform the ion implantation of impurities at a very high acceleration energy and to introduce the impurities into the high-concentration diffusion region 18 by long-time heat treatment. Therefore, manufacturing is not easy. In addition, the impurity concentration reduces in a deepest part of the high-concentration diffusion region 18, so it is likely to increase a resistance value between the drain electrode 15 and the silicon body 1.
The buried conductive layer 20 shown in FIG. 32B can be reduced in resistance as compared with the case of FIG. 32A. However, it is necessary to bury the conductive layer in a trench whose depth is approximately 2 μm to 3 μm. Even when the conductive layer is to be buried in the deep trench, a void occurs in the conductive layer or the film thickness of the conductive layer of the drain electrode becomes insufficient in a step portion. Therefore, it is likely to increase the resistance value.